1. Field of the Invention
The present invention relates to an information processing equipment, such as a personal computer, a work station, and so on. And, it relates to a processor and a control method thereof, including a bus in a system thereof, wherein a bus, in particular, a multiplex bus in which addresses and data are used in time-sharing, supports a burst transfer protocol for enabling transfer of a plurality of write operations onto the addresses being in succession, with a series of continuing data cycles following one address cycle.
2. Description of the Prior Art
In Japanese Patent Laying-Open No. Hei 5-324544 (1993), there is disclosed a technology relating to a computer apparatus having a bus in the system thereof, wherein the bus, being the multiplex bus in which addresses and data are used in time-sharing, supports a burst transfer protocol for enabling the transfer of the plural write operations onto the addresses being in succession with the series of continuing data cycles following one address cycle.
In the conventional technology relating bus systems, in particular, among various standard bus systems, so-called address/data multiplex buses come to be commonly used, upon a requirement of reducing the number of the pins on an interface LSI, in which the address and data are used in the time-sharing manner. And, among such the address/data multiplex buses, for the purpose of improving data efficiency on the bus, many of those buses come to support the burst transfer protocol enabling the transfer of the plural write operations into the continuing addresses in succession with the series of continuing data cycles following one address cycle.
In FIG. 3, in particular, FIG. 3 (a) shows a timing chart for a continuous PIO write transfer, in which, when a single PIO write access (i.e., an access from a processor to an input/output device (IO)) appears four (4) times on the system bus in succession, they are transferred with attaching access addresses to them respectively, and in particular, FIG. 3 (b) shows the timing chart of a burst PIO write transfer access, in which accesses are converted into a burst of four (4) data cycles to be transferred onto the continuing addresses.
In the case of transferring the same continuing four (4) data (D0-D3), although it takes eight (8) clocks by the continuous PIO write transfer method shown in FIG. 3 (a), however, it is possible to transfer them with only five (5) clocks by means of the burst PIO write transfer method shown in FIG. 3 (b). It is appear that the efficiency on data transfer can be improved higher with use of the burst PIO write transfer method.
In the information processing equipment having such the address/data multiplex bus as the system bus thereof, supporting the burst transfer protocol mentioned above, though a module(s) being directly connected to the system bus can issue a plurality of accesses for the continuing addresses with the burst protocol, by supporting the burst protocol, however, with the transfer requirement, being transmitted through a bus converter from a bus of an other hierarchy, for example, a PIO access which is accessed to the system bus through the bus converter from an other processor, it must be issued to the system bus as the single transfer, into which the address cycle is inserted every time even if it is the transfer to the continuous addresses, thereby bringing about a drawback that the data efficiency on the bus is decreased down.
An object of the present invention, accordingly, is to provide a, processor for an information processing equipment and a control method thereof, in which the transfer requirement, being converted to be addressed through the bus converter from the bus of an other hierarchy, such as the PIO access which is accessed to the system bus through the bus converter from an other processor, is issued after being converted into the burst protocol transfer onto the system bus, if it is the transfer for the addresses in succession, thereby preventing from decrease in the data efficiency.
According to the present invention, for achieving the object mentioned in the above, there is provided a system, wherein are provided, a buffer being able to store plural sets of write addresses and data for a system bus; a comparator for deciding whether there are write accesses coming before and after about the time and being continuous in the write addresses thereof, which are stored in said buffer and; means for converting respective writing operations onto the continuing addresses into burst transfer protocol which can be transferred with a series of continuous data cycles following one address cycle, when the comparator, as a result of deciding, finds the ones coming before and after about the time and being continuous in the write addresses thereof.
With such the construction as mentioned in the above, the transfer requirement, being converted to be addressed through the bus converter from the bus of the other hierarchy, such as the PIO access which is accessed to the system bus through the bus converter from the other processor, can be issued after being converted into the burst protocol to be transfered, if it is the transfer for the addresses in successions, thereby bringing about increase in the data efficiency on the system bus and in performance of the system as a whole.